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PIC18F2XK20/4XK20

DS41297F-page 26

Advance Information

2009 Microchip Technology Inc.

4.3

Verify Configuration Bits

A configuration address may be read and output on

PGD via the 4-bit command, ‘1001’. Configuration data

is read and written in a byte-wise fashion, so it is not

necessary to merge two bytes into a word prior to a

compare. The result may then be immediately

compared to the appropriate configuration data in the

programmer’s

memory

for

verification.

Refer

Section 4.1 “Read Code Memory, ID Locations and

Configuration Bits” for implementation details of

reading configuration data.

4.4

Read Data EEPROM Memory

Data EEPROM is accessed one byte at a time via an

Address Pointer (register pair EEADRH:EEADR) and a

data latch (EEDATA). Data EEPROM is read by loading

EEADRH:EEADR with the desired memory location

and initiating a memory read by appropriately configur-

ing the EECON1 register. The data will be loaded into

EEDATA, where it may be serially output on PGD via

the 4-bit command, ‘0010’ (Shift Out Data Holding

falling edge of the 8th PGC of the operand to allow

PGD to transition from an input to an output. During this

time, PGC must be held low (see Figure 4-4).

The command sequence to read a single byte of data

is shown in Table 4-2.

FIGURE 4-3:

READ DATA EEPROM

FLOW

TABLE 4-2:

READ DATA EEPROM MEMORY

Start

Set

Address

Read

Byte

Done

Yes

done?

Move to TABLAT

Shift Out Data

4-bit

Command

Data Payload

Core Instruction

Step 1: Direct access to data EEPROM.

0000

9E A6

9C A6

BCF

EECON1, EEPGD

BCF

EECON1, CFGS

Step 2: Set the data EEPROM Address Pointer.

0000

0E <Addr>

6E A9

OE <AddrH>

6E AA

MOVLW

<Addr>

MOVWF

EEADR

MOVLW

<AddrH>

MOVWF

EEADRH

Step 3: Initiate a memory read.

0000

80 A6

BSF

EECON1, RD

Step 4: Load data into the Serial Data Holding register.

0000

0010

50 A8

6E F5

00 00

MOVF

EEDATA, W, 0

MOVWF TABLAT

NOP

Shift Out Data

(1)

Note

The <LSB> is undefined. The <MSB> is the data.

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